Leupers Rainer

Code Optimization Techniques For Embedded Processors

Code Optimization Techniques For Embedded Processors

Logic Locking

Power Estimation On Electronic System Level Using Linear Power Models

Retargetable Compiler Technology For Embedded Systems

C Compilers For Asips

Programming Heterogeneous Mpsocs

Optimized Asip Synthesis From Architecture Description Language Models

Architecture Exploration For Embedded Processors With Lisa

Integrated System-Level Modeling Of Network-On-Chip Enabled Multi-Processor Platforms

Integrated System-Level Modeling Of Network-On-Chip Enabled Multi-Processor Platforms

Retargetable Processor System Integration Into Multi-Processor System-On-Chip Platforms

Architecture Exploration For Embedded Processors With Lisa

Optimized Asip Synthesis From Architecture Description Language Models

Language-Driven Exploration And Implementation Of Partially Re-Configurable Asips

C Compilers For Asips

Logic Locking

Customizable Embedded Processors

Multiprocessor Systems On Chip

Language-Driven Exploration And Implementation Of Partially Re-Configurable Asips

Retargetable Code Generation For Digital Signal Processors