Leupers Rainer

Retargetable Code Generation For Digital Signal Processors

Code Optimization Techniques For Embedded Processors

Code Optimization Techniques For Embedded Processors

Logic Locking

Power Estimation On Electronic System Level Using Linear Power Models

Retargetable Compiler Technology For Embedded Systems

Application Analysis Tools For Asip Design

Retargetable Compiler Technology For Embedded Systems

C Compilers For Asips

Programming Heterogeneous Mpsocs

Programming Heterogeneous Mpsocs

Optimized Asip Synthesis From Architecture Description Language Models

Architecture Exploration For Embedded Processors With Lisa

Integrated System-Level Modeling Of Network-On-Chip Enabled Multi-Processor Platforms

Integrated System-Level Modeling Of Network-On-Chip Enabled Multi-Processor Platforms

Retargetable Processor System Integration Into Multi-Processor System-On-Chip Platforms

Retargetable Processor System Integration Into Multi-Processor System-On-Chip Platforms

Multiprocessor Systems On Chip

Optimized Asip Synthesis From Architecture Description Language Models

Architecture Exploration For Embedded Processors With Lisa

Language-Driven Exploration And Implementation Of Partially Re-Configurable Asips

Customizable Embedded Processors

Application Analysis Tools For Asip Design

C Compilers For Asips

Multiprocessor Systems On Chip

Language-Driven Exploration And Implementation Of Partially Re-Configurable Asips

Retargetable Code Generation For Digital Signal Processors

Logic Locking