John P Hayes

Hierarchical Modeling For Vlsi Circuit Testing

Design, Analysis And Test Of Logic Circuits Under Uncertainty

Design, Analysis And Test Of Logic Circuits Under Uncertainty

Network Marketing For Dummies

Introductory Phonology

Layout Minimization Of Cmos Cells

Hierarchical Modeling For Vlsi Circuit Testing

Introductory Phonology

The Nevada Buckaroo

Quantum Circuit Simulation

Computer Architecture And Organization