Software and Compilers for Embedded Systems -

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Résumé :
PThis book constitutes the refereed proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2004, held in Amsterdam, The Netherlands, in September 2004./P PThe 17 revised full papers presented were carefully reviewed and selected from close to 50 submissions. The papers are organized in topical sections on application synthesis, data flow analysis, data partitioning, task scheduling, and code generation./P

Sommaire:
Invited Talk.- The New Economics of Embedded Systems.- Application Specific (Co)Design.- A Framework for Architectural Description of Embedded System.- Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.- ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.- System and Application Synthesis.- Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition.- An Integer Linear Programming Approach to Classify the Communication in Process Networks.- Predictable Embedded Multiprocessor System Design.- Data Flow Analysis.- Suppression of Redundant Operations in Reverse Compiled Code Using Global Dataflow Analysis.- Fast Points-to Analysis for Languages with Structured Types.- Data Partitioning.- An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications.- Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization.- On the Phase Coupling Problem Between Data Memory Layout Generation and Address Pointer Assignment.- Task Scheduling.- Dynamic Mapping and Ordering Tasks of Embedded Real-Time Systems on Multiprocessor Platforms.- Integrated Intra- and Inter-task Cache Analysis for Preemptive Multi-tasking Real-Time Systems.- A Fuzzy Adaptive Algorithm for Fine Grained Cache Paging.- Code Generation.- DSP Code Generation with Optimized Data Word-Length Selection.- Instruction Selection for Compilers That Target Architectures with Echo Instructions.- A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor.