Introduction to Noise-Resilient Computing - Yanushkevich, Svetlana N.

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Résumé :
Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work

Biographie:
S. N. Yanushkevich received M.Sc. (1989) and Ph.D. (1992) degrees in electrical and computer engineering from the State University of Informatics and Radioelectronics, Minsk, Belarus, and she received her Habilitation degree (1999) from the University of Technology,Warsaw, Poland. In 2001, she joined the Department of Electrical and Computer Engineering, University of Calgary, Canada, where she is currently Associate Professor. Dr. Yanushkevich is a Senior Member of the IEEE and a Member of the Institute of Electronics, Information and Communication Engineers (IEICE), Japan. In 2011, she was awarded the Invitation Fellowship by the Japan Society for Promotion of Science ( JSPS) and worked at the Research Center for Integrated Quantum Electronics, Hokkaido University. Dr. Yanushkevich took part in several projects on the development of high-performance parallel computing tools for image processing applications. Her current research interests include nanocomputing in 3D and artificial intelligence in decision making. Dr. Yanushkevich serves as a Guest Editor of several international journals, and she was a general chair and co-chair of about 20 international conferences, symposia, and workshops. Dr. Yanushkevich has published over 200 technical papers and patents, and authored, co-authored, and edited books