Legacy Data: A Structured Methodology for Device Migration in DSM Technology - Pallab Chatterjee

. .

Résumé :
Legacy Data: A Structured Methodology For Device Migration in DSM Technology deals with the migration of existing hard IP from one technology to another using repeatable procedures. The challenge of hard IP migration is not simply an EDA problem but rather a client application specification problem. It requires a deep understanding of the process technologies, EDA tools (and their interfaces) and target applications. Legacy Data: A Structured Methodology For Device Migration in DSM Technology is unique in that there are currently no reference books focused on legacy data reuse, especially for hard IP. This book will allow CAD practitioners to quickly develop methodologies that capitalize on the large volumes of legacy data available within a company today. It details the issues of developing a structured methodology, building verification test benches, and validating the final physical design.

Sommaire:
1. Introduction.- 2. Legacy Data.- 2.1 Modem SOCFlow.- 2.2 Legacy Data Review.- 3. Reasons for Data Migration.- 3.1 Functional reuse in derivative products.- 4. New Rules for DSM Flows.- 4.1 Device Geometries.- 4.2 Wafer Type.- 4.3 Isolation technique.- 4.4 Operating Voltage.- 4.5 Process design rules.- 4.6 Device performance.- 4.7 Interconnect options.- 4.8 Memory techniques.- 4.9 OPC masking techniques.- 5. Structured Methodology.- 5.1 Assumptions formigration.- 5.2 Flowchart of methodology.- 5.3 Sequence of the methodology.- 6. Screening Criteria for Blocks.- 6.1 Introduction of Case Study.- 6.2 Block Selection.- 6.3 Description of Selection Criteria.- 7. Process Compatibility.- 7.1 Process migration tradeoffs.- 7.2 Sample USB block tradeoff analysis.- 8. Test Bench Requirements.- 8.1 Test bench minimum requirements.- 8.2 Digital Test Bench.- 8.3 Device Level Test Bench.- 8.4 USB Sample Summary.- 9. Block Identification.- 9.1 Physical and Design Views.- 9.2 Multiple View Correction.- 9.3 Hierarchy Tree.- 9.4 Test Circuits, Clocks and Power Grids.- 10. Design Retargeting.- 10.1 Device Level Re-Design Stages.- 10.2 Re-Engineering Process - Device Level Design.- 10.3 Re-Engineering Process - Corner Based Design.- 10.4 Summary for USB Block Migration.- 11. Design Validation.- 11.1 Types of Validation.- 11.2 Case Study Validation Summary.- 12. Physical Design Migration.- 12.1 Physical Migration Options.- 13. Post Layout Validation Ill.- 13.1 Design Rule Checking - DRC Ill.- 13.2 Layout Vs. Schematic - LVS.- 13.3 Power Analysis - IR Drop.- 13.4 Noise Analysis and Coupling - Signal Integrity.- 13.5 RC Extraction for STA & for Device Simulation.- 13.6 Case Study Summary for Physical Verification.- 14. Full Chip Verification.- 14.1 Abstracts Required.