Advanced Semiconductor Memories - Sharma, Ashok K

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Résumé :

PREFACE xix

1 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES 1

1.1. Semiconductor Memories Overview 1

1.2. Advanced Semiconductor Memory Developments 8

1.3. Future Memory Directions 16

References 18

2 STATIC RANDOM ACCESS MEMORY TECHNOLOGIES 19

2.1. Basic SRAM Architecture and Cell Structures 19

2.1.1. SRAM Performance and Timing Specifications 21

2.1.2. SRAM ReadWrite Operations 23

2.2. SRAM Selection Considerations 26

2.3. High Performance SRAMs 33

2.3.1. Synchronous SRAMs Flow-Through 41

2.3.2. Zero Bus Turnaround SRAMs 43

2.3.3. Quad Data Rate SRAM 44

2.3.4. Double Data Rate SRAM 50

2.3.5. No-Turnaround Random Access Memory 51

2.4. Advanced SRAM Architectures 55

2.5. Low-Voltage SRAMs 61

2.6. BiCMOS Technology SRAMs 75

2.7. SOI SRAMs 79

2.8. Specialty SRAMs 91

2.8.1. Multiport RAMs 92

2.8.1.1. Dual-Port RAMs 92

2.8.1.2. Quadport(TM) RAMs 101

2.8.2. First-In-First-Out (FIFO) Memories 103

2.8.3. Content Addressable Memories (CAMs) 111

2.8.3.1. Advanced Content Addressable Memories (Examples) 116

References 122

3 HIGH-PERFORMANCE DYNAMIC RANDOM ACCESS MEMORIES 129

3.1. DRAM Technology Evolution and Trends 129

3.2. DRAM Timing Specifications and Operations 133

3.2.1. General Timing Specifications 133

3.2.2. Memory Read Operation 135

3.2.3. Memory Write Operation 138

3.2.4. Read-Modify-Write Operation 140

3.2.5. DRAM Refresh Operation 141

3.3. Extended-Data-Out DRAMS 145

3.3.1. EDO DRAM (Example) 145

3.4. Enhanced DRAM (EDRAM) 146

3.5. Synchronous DRAMGRAM Architectures 150

3.5.1. SDR SDRAMSGRAM 150

3.5.2. DDR SDRAMSGRAM Features 151

3.5.3. Synchronous DRAM 256Mb (Example) 154

3.5.3.1. Initialization 154

3.5.3.2. Register Definition 155

3.5.3.3. Commands 157

3.5.3.4. SDRAM Operations 159

3.6. Enhanced Synchronous DRAM (ESDRAM) 163

3.7. Cache DRAM (CDRAM) 166

3.8. Virtual Channel Memory (VCM) DRAMs 172

3.9. Advaned DRAM Technology Perspectives 175

3.9.1. Memory Capacitor Cell Improvements 179

3.9.2. 64-Mb DRAMs 188

3.9.3. 256-Mb DRAMs 195

3.10. Gigabit DRAM Scaling Issues and Architectures 200

3.11. Multilevel Storage DRAMs 217

3.12. SOI DRAMs 221

References 231

4 APPLICATION-SPECIFIC DRAM ARCHITECTURES AND DESIGNS 237

4.1. Video RAMs (VRAMs) 241

4.2. Synchronous Graphic RAMs (SGRAMs) 244

4.2.1. 64-Mb DDR SGRAM 246

4.2.2. 256-Mb DDR Fast Cycle RAM 253

4.3. Rambus Technology Overview 257

4.3.1. Direct RDRAM Technologies and Architectures 264

4.3.2. Direct Rambus Memory System-Based Designs 272

4.4. Synchronous Link DRAMs (SLDRAMs) 275

4.4.1. SLDRAM Standard 277

4.4.2. SLDRAM Architectural and Functional Overview 283

4.4.3. SLDRAM (Example) 285

4.5. 3-D RAM 296

4.5.1. Pixel ALU Operations 305

4.6. Memory System Design Considerations 309

References 316

5 ADVANCED NONVOLATILE MEMORY DESIGNS AND TECHNOLOGIES 319

5.1. Nonvolatile Memory Advances 319

5.1.1. Introduction 319

5.1.2. Serial EEPROMs 323

5.1.3. Flash Memory Developments 327

5.2. Floating Gate Cell Theory and Operations 334

5.2.1. Floating Gate Cell Theory 334

5.2.2. Charge Transport Mechanisms 339

5.2.2.1. Fowler-Nordheim Tunneling 340

5.2.2.2. Polyoxide Conduction 342

5.2.2.3. Channel Hot-Electron Injection (CHEI) 343

5.2.2.4. Direct Band-to-Band T...

Sommaire:
ASHOK K. SHARMA is the author of Semiconductor Memories: Technology, Testing, and Reliability (Wiley-IEEE Press, 1997). He is currently working as a reliability engineering manager at NASA, Goddard Space Flight Center, Greenbelt, Maryland....