Digital System Design Using Fsms - Minns, Peter D

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Auteur(s) : Minns, Peter D

Editeur : Wiley

Langue : Anglais

Parution : 01/06/2021

Format : Moyen, de 350g à 1kg

Nombre de pages : 352.0

Expédition : 792

Dimensions : 25.0 x 17.5 x 2.4

ISBN : 9781119782704

Résumé :
DIGITAL SYSTEM DESIGN USING FSMS

Explore this concise guide perfect for digital designers and students of electronic engineering who work in or study embedded systems

Digital System Design using FSMs: A Practical Learning Approach delivers a thorough update on the author's earlier work, FSM-Based Digital Design using Verilog HDL. The new book retains the foundational content from the first book while including refreshed content to cover the design of Finite State Machines delivered in a linear programmed learning format. The author describes a different form of State Machines based on Toggle?Flip Flops and Data Flip Flops.

The book includes many figures of which 15 are Verilog HDL simulations that readers can use to test out the design methods described in the book, as well as 19 Logisim simulation files with figures. Additional circuits are also contained within the Wiley web folder. It has tutorials and exercises, including comprehensive coverage of real-world examples demonstrated alongside the frame-by-frame presentations of the techniques used.

In addition to covering the necessary Boolean algebra in sufficient detail for the reader to implement the FSM based systems used in the book, readers will also benefit from the inclusion of:

• A thorough introduction to finite-state machines and state diagrams for the design of electronic circuits and systems
• An exploration of using state diagrams to control external hardware subsystems
• Discussions of synthesizing hardware from a state diagram, synchronous and asynchronous finite-state machine designs, and testing finite-state machines using a test-bench module
• A treatment of the One Hot Technique in finite-state machine design
• An examination of Verilog HDL, including its elements
• An analysis of Petri-Nets including both sequential and parallel system design

Suitable for design engineers and senior technicians seeking to enhance their skills in developing digital systems, Digital System Design using FSMs: A Practical Learning Approach will also earn a place in the libraries of undergraduate and graduate electrical and electronic engineering students and researchers....

Biographie:

Peter D. Minns, PhD, now retired, has over 33 years experience as an academic Senior Lecturer, most recently in the Department of Mathematics, Physics, and Electrical Engineering at Northumbria University at Newcastle, UK. Prior to academia, he worked in the telecommunications industry and in Power System Protection as a Design and Development Engineer.

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Sommaire:

Preface viii

Acknowledgements x

About the Companion Website xi

Guide to Supplementary Resources xii

1 Introduction to Finite State Machines 1

1.1 Some Notes on Style 1

2 Using FSMs to Control External Devices 25

2.1 Introduction 25

3 Introduction to FSM Synthesis 45

3.1 Introduction 45

3.2 Tutorials Covering Chapters 1, 2, and 3 71

3.2.1 Binary data serial transmitter FSM 71

3.2.2 The high low FSM system 76

3.2.3 The clocked watchdog timer FSM 80

3.2.3.1 FSM equations 81

3.2.4 The asynchronous receiver system clocked FSM 84

3.2.4.1 Brief note on the development of the test bench generator 86

3.2.4.2 The state diagram 86

3.2.4.3 The state diagram equations 87

3.2.4.4 The outputs 87

3.2.4.5 Verilog HDL simulation of the completed system 95

4 Asynchronous FSM Methods 97

4.1 Introduction to Asynchronous FSM 97

4.2 Summary 144

4.3 Tutorials 144

4.3.1 FSM motor with fault detection 144

4.3.2 The mower in four and two states 148

5 Clocked One Hot Method of FSM Design 153

5.1 Introduction 153

5.2 Tutorials on the Clocked One Hot FSM Method 168

5.2.1 Seven-state system clocked one hot method 168

5.2.2 Memory tester FSM 170

5.2.3 Eight-bit sequence detector FSM 174

6 Further Event-Driven FSM Design 179

6.1 Introduction 179

6.2 Conclusions 195

7 Petri Net FSM Design 197

7.1 Introduction 197

7.2 Tutorials Using Petri Net FSM 234

7.2.1 Controlled shared resource Petri nets 234

7.2.2 Serial clock-driven Petri net FSM 240

7.2.3 Using asynchronous (event-driven) design with Petri nets 247

7.3 Conclusions 249

Appendix A1: Boolean Algebra 251

A1.1 Basic Gate Symbols 251

A1.2 The Exclusive OR and Exclusive NOR 252

A1.3 Laws of Boolean Algebra 252

A1.3.1 Basic OR rules 252

A1.3.2 Basic AND rules 253

A1.3.3 Associative and commutative laws 253

A1.3.4 Distributive laws 253

A1.3.5 Auxiliary rule for static 1 hazard removal 254

A1.3.5.1 Proof of the Auxiliary Rule 254

A1.3.6 Consensus theorem 254

A1.3.7 The effect of signal delay in logic gates 255

A1.3.8 De-Morgan's theorem 256

A1.4 Examples of Applying the Laws of Boolean Algebra 257

A1.4.1 Converting AND-OR to NAND 257

A1.4.2 Converting AND-OR to NOR 257

A1.4.3 Logical adjacency rule 258

A1.5 Summary 258

Appendix A2: Use of Verilog HDL and Logisim to FSM 261

A2.1 The Single-Pulse Generator with Memory Clock-Driven FSM 261

A2.2 Test Bench Module and its Purpose 267

A2.3 Using Synapticad Software 268

A2.4 More Direct Method 270

A2.5 A Very Simple Guide to Using the Logisim Simulator 271

A2.5.1 The Logisim top level menu items 271

A2.6 Using Flip-Flops in a Circuit 273

A2.7 Example Single-Pulse FSM 275

A2.8 How to Use the Simulator to Simulate the Single-Pulse FSM 278

A2.8.1 Using Logisim with the truth table approach 278

A2.9 Using Logisim with the Truth Table Approach 279

A2.9.1 Useful note 281

A2.10 Summary 281

Appendix A3: Counters, Shift Registers, Input, and Output with an FSM 285

A3.1 Basic Down Synchronous Binary Counter Development 285

A3.2 Example of a Four-Bit Synchronous Up Counter with T Type Flip-Flops 288

A3.3 Parallel Loading Counters - Using T Flip-Flops 291

A3.4 Using D Flip-Flops To Build Parallel Loading Counters 292

A3.5 Simple Binary Up Counter with Parallel Inp...