Full-Chip Nanometer Routing Techniques - Ho, Tsung-Yi

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Résumé :
At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Biographie:
digital microfluidics, biochips, and cyberphysical systems...

Sommaire:
Kai Hu received his B. Sci. degree from Fudan University, Shanghai, China, in 2009, and the M.S. and Ph.D. degree from Duke University, NC, USA, in 2011 and 2015, respectively. He was the recipient of the VLSI Test Symposium (VTS) Best Paper Award in 2013, IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award in 2015, and European Design and Automation Association (EDAA) Outstanding Dissertation Award in 2016. He is currently a Senior Engineer with Oracle. Inc., Santa Clara, CA, USA. His current research interests include algorithms for computer-aided design and testing of flow-based microfluidic biochips. Krishnendu Chakrabarty is the William H. Younger Distinguished Professor of Engineering in the Department of Electrical and Computer Engineering, at Duke University in Durham, NC. He has been at Duke University since 1998. His current research is focused on: testing and design-for-testability of integrated circuits (especially 3D and multicore chips)...