Hardware Component Modeling -

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Sommaire:
1. The History of Vital: VHDL Asic Library Update.- 1.1. Introduction.- 1.2. VITAL Development.- 1.3. VITAL Principles.- 1.4. Market Impact.- 1.5. Observations.- 1.6. Summary.- 2. Issues in Efficient Modeling and Acceleration of Vital Models.- 2.1. Introduction.- 2.2. Overview of a VITAL Level-1 Architecture.- 2.3. Impact of Modeling Styles on Simulation Performance.- 2.4. Elements of Acceleration.- 2.5. Acceleration Strategies.- 2.6. Impact of Implementation Technologies.- 2.7. Conclusions.- 3. Standards for Interoperability and Portability.- 3.1. Introduction.- 3.2. Design Methodology with VHDL.- 3.3. Requirements for Design for Durability.- 3.4. Requirements for Board Level Simulation.- 3.5. Conclusion.- 4. Abstract Data Types and the Digital System Description and Simulation Environments.- 4.1. Introduction.- 4.2. Background and Related Work.- 4.3. Extended VHDL Packages.- 4.4. Finite State Machines (FSMs).- 4.5. The Description of Clocks.- 4.6. Petri Nets.- 4.7. Conclusions.- 5. Modeling Highly Flexible and Self-Generating Parameterizable Components in VHDL.- 5.1. Introduction.- 5.2. Fundamentals.- 5.3. Modeling of Different Parameter Classes in VHDL.- 5.4. Case Study.- 5.5. Functional Verification of Parameterizable Components.- 5.6. Conclusion.- 5.7. Acknowledgments.- 6. Melody: An Efficient Layout-Based Model Generator.- 6.1. Introduction.- 6.2. The Generation of Structural Models.- 6.3. Functional Simulation.- 6.4. Experiments.- 6.5. Conclusion.- 7. Quality Measures & Analysis: A Way to Improve VHDL Models.- 7.1. Introduction.- 7.2. The SAVE Project.- 7.3. Efficiency.- 7.4. Complexity Analysis.- 7.5. Synthesizability.- 7.6. Conclusions.- 8. Modern Concepts of Quality and Their Relationship to Design Reuse and Model Libraries.- 8.1. Introduction.- 8.2. Quality.-8.3. Quality-Driven Design.- 8.4. Design Reuse.- 8.5. Quality-Driven Design and Model Libraries.- 8.6. Validation of Library Models.- 8.7. Conclusion.