Soc Design Methodologies -

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Sommaire:
Architecture for Signal & Image Processing.- Two ASIC for Low and Middle Levels of Real Time Image Processing.- 64 ? 64 Pixels General Purpose Digital Vision Chip.- A Vision System on Chip for Industrial Control.- Fast Recursive Implementation of the Gaussian Filter.- Dynamically Re-configurable Architectures.- A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.- Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.- Reconfigurable Architecture Using High Speed FPGA.- CAD Tools.- Design Technology for Systems-on-Chip.- Distributed Collaborative Design over Cave2 Framework.- High Performance Java Hardware Engine and Software Kernel for Embedded Systems.- An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures.- Interconnect Capacitance Modelling in a VDSM CMOS Technology.- IP Design & Reuse.- Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design.- An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms.- Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 ?m Bulk and Silicon-On-Insulator CMOS Technologies.- High Level Design Methodologies.- A Standardized Co-simulation Backbone.- Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory.- Power Issues.- Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model.- Power Consumption Model for the DSP OAK Processor.- Design for Specific Constraints.- Integration of Robustness in the Design of a Cell.- Impact of Technology Spreading on MEMS design Robustness.- Architectures.- A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation.-Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder.- Low Power, Low Voltage.- Low-Voltage Embedded-RAM Technology: Present and Future.- Low-Voltage 0,25 ?m CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.- Gate Sizing for Low Power Design.- Timing Issues.- Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.- Feasible Delay Bound Definition.- Advance in Mixed Signal.- CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors.- A VHDL-AMS Case Study: The Incremental Design of an Efficient 3rd Generation MOS Model of a Deep Sub Micron Transistor.- Verification & Validation.- Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths.- Functional Test Generation using Constraint Logic Programming.- Test.- An Industrial Approach to Core-Based System Chip Testing.- Power-Constrained Test Scheduling for SoCs Under a no session Scheme.- Random Adjacent Sequences: An Efficient Solution for Logic BIST.- On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.- Built-in Test of Analog Non-Linear Circuits in a SOC Environment.- Sensors.- Design of a Fast CMOS APS Imager for High Speed Laser Detections.- Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing.- Authors Index.- Keywords Index.