Quick Start Guide to Verilog - Brock J. Lameres

. .

Auteur(s) : Brock J. Lameres

Editeur : Springer International Publishing

Langue : Anglais

Parution : 01/03/2019

Expédition : 637

Dimensions : 26.0 x 18.3 x 1.6

ISBN : 3030105512

Résumé :
This textbook provides a starter?s guide to Verilog, to be used in conjunction with a one-semester course in Digital Systems Design, or on its own for readers who only need an introduction to the language. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the presentation with learning goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to ?d? after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.

Written the way the material is taught, enabling a bottom-up approach to learning which culminates with a high-level of learning, with a solid foundation; Emphasizes examples from which students can learn: contains a solved example for nearly every section in the book; Includes more than 200 exercise problems, as well as concept check questions for each section, tied directly to specific learning outcomes.

Biographie:

Brock LaMeres joined the Montana State ECE faculty in July of 2006. He received his Ph.D. in electrical engineering from the University of Colorado, Boulder in December of 2005, his MSEE from the University of Colorado, Colorado Springs in May of 2001, and his BSEE from Montana State University, Bozeman in December of 1998. LaMeres teaches and conducts research in the area of digital systems with particular emphasis on exploiting reprogrammable fabrics to deliver more effective computer systems. LaMeres is also studying how engineering education can be improved using innovative e-learning environments.

LaMeres has published over 70 manuscripts and 2 textbooks in the area of high speed digital systems. LaMeres has also been granted 13 US patents in the area of digital signal propagation. LaMeres is a Senior Member of IEEE and a Registered Professional Engineer in the States of Montana and Colorado. Dr. LaMeres is a member of AESS, ASEE and serves as the faculty advisor of the student branch of IEEE at MSU.

Prior to coming to MSU, Dr. LaMeres worked as an R&D engineer for Agilent Technologies in Colorado Springs, CO from 1999 to 2006. LaMeres was a hardware design engineer in the Logic Analysis R&D lab. He designed acquisition hardware for the 16910/11/12 and 16950 Logic Analyzer systems in addition to developing a variety of probing solutions.

Sommaire:
The Modern Digital Design Flow.- Verilog Constructs.- Modeling Concurrent Functionality in Verilog.- Structural Design and Hierarchy.- Modeling Sequential Functionality.- Test Benches.- Modeling Sequential Storage and Registers.- Modeling Finite State Machines.- Modeling Counters.- Modeling Memory.- Computer System Design.