Quality-Driven SystemC Design - Drechsler, Rolf

. .

Résumé :
A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.

Biographie:
Lucas Klemmer received the M.Sc. degree in computer science from the University of Bremen, Germany, in 2020. Afterwards, he started as a PhD student with the Institute for Complex Systems, Johannes Kepler University Linz, Austria and received his PhD in computer science in 2024. He is currently working as a Postdoc at the same institute. He published several papers at international conferences and journals, such as ASP-DAC, DATE, DAC, FDL, and TCAD. His current research interests include RISC-V, the waveform-based analysis of hardware designs, and novel applications for formal methods in the verification and synthesis domains. He received the Best Paper Award at FDL 2022 and the JKU Young Researchers' Award for his PhD thesis in 2024. Daniel Gro?e received the Dr.-Ing. Degree in computer science from the University of Bremen in 2008. He remained as a Post-Doctoral Researcher with the Group of Computer Architecture, University of Bremen. In 2010, he was a substitute Professor for computer architecture with the University of Freiburg, Germany. From 2013 to 2014, he was the CEO of the EDA start-up solvertec focusing on automated debugging techniques. After that, until 2020, he was a Senior Researcher at the University of Bremen as well as Scientific Coordinator of the Graduate School System Design funded within the German Excellence Initiative. In addition, he has been working at the German Research Center for Artificial Intelligence (DFKI) since 2015. In July 2020, he became a full professor at the Johannes Kepler University Linz, Austria, where he is the head of the Institute for Complex Systems as well as the head of the LIT Secure and Correct Systems Lab (composing the expertise of over ten JKU institutes) since 2022. His current research interests include verification, virtual prototyping, debugging, synthesis and RISC-V. He published over 170 papers in peer-reviewed journals and conferences in the above areas. Dr. Gro?e served in program committees of numerous conferences, including ASP-DAC, DAC, DATE, ICCAD, CODES+ISSS, GLSVLSI, FDL, ETS, and MEMOCODE and was the General Chair of FDL 2022. He received best paper awards (FDL 2007, DVCon Europe 2018, ICCAD 2018, FDL 2020 and FDL 2022) as well as business-related awards (IKT Innovativ Award 2013, Weconomy Award 2013, and Embedded Award 2014). He is an IEEE Senior Member and an Allied Member of the Accellera Systems Initiative in the SystemC Verification Working Group....

Sommaire:
Dedication. List of Figures. List of Tables. Preface. Acknowledgments. 1. INTRODUCTION. 2. PRELIMINARIES. 2.1 Boolean Reasoning. 2.2 Circuits. 2.3 Formal Verification. 2.4 SystemC. 3. SYSTEM-LEVEL VERIFICATION. 3.1 Constraint-based Simulation. 3.2 Improvements for Constraint-based Simulation. 3.3 Contradiction Analysis for Constraint-based Simulation. 3.4 Measuring the Quality of Testbenches. 3.5 Summary and Future Work. 4. BLOCK-LEVEL VERIFICATION. 4.1 Property Checking. 4.2 Acceleration of Iterative Property Checking. 4.3 Contradictory Antecedent Debugging for Property Checking. 4.4 Analyzing Functional Coverage in Property Checking. 4.5 Summary and Future Work. 5. TOP-LEVEL VERIFICATION. 5.1 Checker Generation. 5.2 HW/SW Co-Verification for Embedded Systems. 5.3 Summary and Future Work. 6. SUMMARY AND CONCLUSIONS. References. Index.