Interconnect-Centric Design for Advanced SOC and NOC -

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Résumé :
In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

Sommaire:
Preface 1.Introduction Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, Axel Jantsch 2. System-on-Chip Challenges in the Deep-Submicron Era Jan M. Rabaey PART I: PHYSICAL AND ELECTRICAL ISSUES 3. Wires as Interconnects Li-Rong Zheng, Hannu Tenhunen 4. Global Interconnect Analysis Towards NoC Tero Nurmi, Jian Liu, Dinesh Pamunuwa, Tapani Ahonen, Li-Rong Zheng, Jouni Isoaho, Hannu Tenhunen 5. Design Methodologies for On-Chip Inductive Interconnect Magdy A. El-Moursy, Eby Friedman 6. Clock Generation and Distribution for High-Performance SoC Designs Stefan Rusu PART II: LOGICAL AND ARCHITECTURAL ISSUES 7. Error-Tolerant Interconnect Schemes Heiko Zimmer, Axel Jantsch 8. Power Reduction Coding for Buses Paul P. Sotiriadis 9. Overview of SoC Buses Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. H?m?l?inen 10. From Buses to Networks David Siguenza Tortosa, Jari Nurmi 11. Arbitration and Routing Schemes for On-Chip Packet Networks Heikki Kariniemi, Jari Nurmi PART III: DESIGN METHODOLOGY AND TOOLS 12. Methodology and Techniques for Noise Reduction in SoC Interconnects Pasi Liljeberg, Johanna Tuominen, Sampo Tuuna, Juha Plosila, Jouni Isoaho 13. Formal Communication Modeling and Refinement Juha Plosila, Tiberiu Seceleanu, Kaisa Sere 14. High-Level Communication Models for On-Chip Multiprocessor System Simulation Jan Madsen, Shankar Mahadevan, Kashif Virk 15. Socket-based Design Using Decoupled Interconnects Drew Wingard PART IV: APPLICATION CASES 16. Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV Kees Goossens, Om. Prajash Gangwal, Jens R?ver, A.P. Niranjan 17. A Brunch for the Coffee Table - Case Study in NOC Platform Design Tapani Ahonen, Seppo Virtanen, Juha Kylli?inen, Dragos Truscan, Tuukka Kasanko, DavidSig?enza Tortosa, Tapio Ristim?ki, Jani Paakkulainen, Tero Nurmi, Ilkka Saastamoinen, Hannu Is?nn?inen, Johan Lilius, Jari Nurmi, Jouni Isoaho