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A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures - Dunn, Ian N.

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    Brand new, In English, Fast shipping from London, UK; Tout neuf, en anglais, expédition rapide depuis Londres, Royaume-Uni;ria9781461346586_dbm

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        Présentation A Parallel Algorithm Synthesis Procedure For High - Performance Computer Architectures Format Broché

         - Livre Littérature Générale

        Livre Littérature Générale - Dunn, Ian N. - 01/09/2012 - Broché - Langue : Anglais

        . .

      • Auteur(s) : Dunn, Ian N. - Meyer, Gerard G. L.
      • Editeur : Springer Us, New York, N.Y.
      • Langue : Anglais
      • Parution : 01/09/2012
      • Format : Moyen, de 350g à 1kg
      • Nombre de pages : 124
      • Expédition : 201
      • Dimensions : 23.5 x 15.5 x 0.8
      • ISBN : 9781461346586



      • Résumé :
        Despite five decades of research, parallel computing remains an exotic, frontier technology on the fringes of mainstream computing. Its much-heralded triumph over sequential computing has yet to materialize. This is in spite of the fact that the processing needs of many signal processing applications continue to eclipse the capabilities of sequential computing. The culprit is largely the software development environment. Fundamental shortcomings in the development environment of many parallel computer architectures thwart the adoption of parallel computing. Foremost, parallel computing has no unifying model to accurately predict the execution time of algorithms on parallel architectures. Cost and scarce programming resources prohibit deploying multiple algorithms and partitioning strategies in an attempt to find the fastest solution. As a consequence, algorithm design is largely an intuitive art form dominated by practitioners who specialize in a particular computer architecture. This, coupled with the fact that parallel computer architectures rarely last more than a couple of years, makes for a complex and challenging design environment. To navigate this environment, algorithm designers need a road map, a detailed procedure they can use to efficiently develop high performance, portable parallel algorithms. The focus of this book is to draw such a road map. The Parallel Algorithm Synthesis Procedure can be used to design reusable building blocks of adaptable, scalable software modules from which high performance signal processing applications can be constructed. The hallmark of the procedure is a semi-systematic process for introducing parameters to control the partitioning and scheduling of computation and communication. This facilitates the tailoring of software modules to exploit different configurations of multiple processors, multiple floating-point units, and hierarchical memories. To showcase the efficacy of this procedure, the book presents threecase studies requiring various degrees of optimization for parallel execution.

        Sommaire:
        1. Introduction.- Notation and Conventions.- Organization.- 2. Parallel Computing.- 1 Architectures.- 2 Programming Models.- 3 Performance Metrics.- 3. Parallel Algorithm Synthesis Procedure.- 1 Architectural Model for Algorithm Synthesis.- 2 Synthesis Procedure.- 3 Related Work.- 4. Review of Matrix Factorization.- 1 Givens-based Solution Procedures.- 2 Householder-based Solution Procedures.- 5. Case Study 1: Parallel Fast Givens QR.- 1 Parallel Fast Givens Algorithm.- 2 Communication Procedures.- 3 Related Work.- 4 Experimental Results.- 6. Case Study 2: Parallel Compact WY QR.- 1 Parallel Compact WY Algorithm.- 2 Related Work.- 3 Experimental Results.- 7. Case Study 3: Parallel Bidiagonalization.- 1 Parallel Matrix Bidiagonalization Algorithm.- 2 Related Work.- 3 Experimental Results.- 8. Conclusion.- References.

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