Application Specific Processors -

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Résumé :
Application Specific Processors is written for use by engineers who are developing specialized systems (application specific systems). Traditionally, most high performance signal processors have been realized with application specific processors. The explanation is that application specific processors can be tailored to exactly match the (usually very demanding) application requirements. The result is that no `processing power' is wasted for unnecessary capabilities and maximum performance is achieved. A disadvantage is that such processors have been expensive to design since each is a unique design that is customized to the specific application. In the last decade, computer-aided design systems have been developed to facilitate the development of application specific integrated circuits. The success of such ASIC CAD systems suggests that it should be possible to streamline the process of application specific processor design. Application Specific Processors consists of eight chapters which provide a mixture of techniques and examples that relate to application specific processing. The inclusion of techniques is expected to suggest additional research and to assist those who are faced with the requirement to implement efficient application specific processors. The examples illustrate the application of the concepts and demonstrate the efficiency that can be achieved via application specific processors. The chapters were written by members and former members of the application specific processing group at the University of Texas at Austin. The first five chapters relate to specific arithmetic which often is the key to achieving high performance in application specific processors. The next two chapters focus on signal processing systems, and the final chapter examines the interconnection of possibly disparate elements to create systems.

Sommaire:
1. Variable-Precision, Interval Arithmetic Processors.- 1.1 Introduction.- 1.2 Variable-Precision, Interval Arithmetic.- 1.3 Previous Research.- 1.4 Processor Implementation.- 1.5 Area, Delay and Execution Time Estimates.- 1.6 Variable-Precision, Interval Arithmetic Algorithms.- 1.7 Conclusions.- 2. Modeling the Power Consumption of CMOS Arithmetic Elements.- 2.1 Introduction.- 2.2 Previous Research.- 2.3 Parallel Adders.- 2.4 Parallel Multipliers.- 2.5 Conclusions.- 3. Fault Tolerant Arithmetic.- 3.1 Introduction.- 3.2 Previous Research.- 3.3 The Time Shared TMR Technique.- 3.4 VLSI Designs and Performance Evaluations.- 3.5 Conclusions.- 4. Low Power Digital Multipliers.- 4.1 Introduction.- 4.2 Related Research.- 4.3 Digital Multipliers.- 4.4 CMOS Multipliers.- 4.5 Combinational Self-Timed Multipliers with Bypassing Logic.- 4.6 Results.- 5. A Unified View of CORDIC Processor Design.- 5.1 Introduction.- 5.2 The CORDIC Algorithm.- 5.3 Combined Architectures.- 5.4 Pipelined Architectures.- 5.5 Architectural Evaluation.- 5.6 Design Guidelines and Conclusions.- 6. Multidimensional Systolic Arrays for Computing Discrete Fourier Transforms and Discrete Cosine Transforms.- 6.1 Introduction.- 6.2 Multidimensional DFT and DCT by Multidimensional Systolic Array.- 6.3 Fast Fourier Transform Computation by Multidimensional Systolic Array.- 6.4 Prime-Factor Decomposed Computation by Multidimensional Systolic Array.- 6.5 Conclusions.- 7. Parallel Implementation of a Fast Third-Order Volterra Filtering Algorithm.- 7.1 Introduction.- 7.2 Volterra Filtering in the Time and Frequency Domain.- 7.3 Parallel Implementation on DSPS.- 7.4 Performance Evaluation.- 7.5 Applications to Nonlinear Communication Channels.- 7.6 Future Research.- 8. Design and Implementation of an Interface Control Unit for Rapid Prototyping.- 8.1 Introduction.- 8.2 Related Work.- 8.3 Interface Control Unit.- 8.4 ICU Protocol.- 8.5 Hardware Design of the ICU.- 8.6 Conclusions.