FPGA Prototyping by SystemVerilog Examples - Pong P. Chu

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Auteur(s) : Pong P. Chu

Editeur : Wiley

Langue : Anglais

Parution : 30/04/2018

Nombre de pages : 652

Expédition : 1404

Dimensions : 26.0 x 18.3 x 3.9

ISBN : 1119282667

Résumé :

A hands-on introduction to FPGA prototyping and SoC design

This is the successor edition of the popular FPGA Prototyping by Verilog Examples text. It follows the same learning-by-doing approach to teach the fundamentals and practices of HDL synthesis and FPGA prototyping. The new edition uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow the strict design guidelines and coding practices used for large, complex digital systems.

The book is completely updated and uses the SystemVerilog language, which absorbs the Verilog language. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software programmability and develop complex and interesting embedded system projects. The new edition:

• Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I2C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
• Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelope generator.
• Expands the original video controller into a complete stream based video subsystem that incorporates a video synchronization circuit, a test-pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.
• Provides a detailed discussion on blocking and nonblocking statements and coding styles.
• Describes basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.
• Provides an overview of bus interconnect and interface circuit.
• Presents basic embedded system software development.
• Suggests additional modules and peripherals for interesting and challenging projects.

FPGA Prototyping by SystemVerilog Examples makes a natural companion text for introductory and advanced digital design courses and embedded system courses. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.

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Biographie:

PONG P. CHU, PhD is an Associate Professor in the Department of Electrical Engineering and Computer Science at Cleveland State University, Cleveland, Ohio. He has taught undergraduate and graduate digital systems and computer architecture courses for more than two decades, and has received multiple instructional grants from the National Science Foundation....

Sommaire:

Preface xxvii

Acknowledgments xxxiii

PART I BASIC DIGITAL CIRCUITS DEVELOPMENT

1 Gate-Level Combinational Circuit 1

1.1 Introduction 1

1.1.1 Brief history of Verilog and SystemVerilog 1

1.1.2 Book coverage 2

1.2 General description 3

1.3 Basic lexical elements and data types 4

1.3.1 Lexical elements 4

1.3.2 Data types used in the book 5

1.3.3 Number representation 6

1.3.4 Operators 7

1.4 Program skeleton 7

1.4.1 Port declaration 7

1.4.2 Signal declaration 8

1.4.3 Program body 8

1.4.4 Concurrent semantics 9

1.4.5 Another example 10

1.5 Structural description 10

1.6 Top-level signal mapping 13

1.7 Testbench 14

1.8 Bibliographic notes 16

1.9 Suggested experiments 16

1.9.1 Code for gate-level greater-than circuit 17

1.9.2 Code for gate-level binary decoder 17

2 Overview of FPGA and EDA Software 19

2.1 FPGA 19

2.1.1 Overview of a general FPGA device 19

2.1.2 Overview of the Xilinx Artix-7 devices 20

2.2 Overview of the Digilent Nexys 4 DDR board 21

2.3 Development flow 22

2.4 Xilinx Vivado Design Suite 24

2.5 Bibliographic notes 24

2.6 Suggested experiments 24

2.6.1 Gate-level greater-than circuit 24

2.6.2 Gate-level binary decoder 26

3 RT-Level Combinational Circuit 29

3.1 Operators 29

3.1.1 Arithmetic operators 31

3.1.2 Shift operators 31

3.1.3 Relational and equality operators 32

3.1.4 Bitwise, reduction, and logical operators 32

3.1.5 Concatenation and replication operators 33

3.1.6 Conditional operators 34

3.1.7 Operator precedence 35

3.1.8 Expression bit-length adjustment 35

3.1.9 Synthesis of z and x values 36

3.2 Always block for a combinational circuit 38

3.2.1 Overview of always block 39

3.2.2 Procedural assignment 40

3.2.3 Conceptual examples 40

3.3 Coding guidelines 43

3.4 If statement 43

3.4.1 Syntax 43

3.4.2 Examples 44

3.5 Case statement 45

3.5.1 Syntax 45

3.5.2 Examples 46

3.5.3 The casez and casex statements 47

3.5.4 Full case and parallel case 48

3.6 Routing structure of conditional control constructs 49

3.6.1 Priority routing network 49

3.6.2 Multiplexing network 51

3.7 Additional coding guidelines for an always block 52

3.7.1 Common errors in combinational circuit codes 52

3.7.2 Guidelines 56

3.8 Parameter and constant 56

3.8.1 Constant 56

3.8.2 Parameter 58

3.9 Replicated structure 59

3.9.1 Generate-for statement 59

3.9.2 Procedural-for statement 60

3.9.3 Example 60

3.10 Design examples 62

3.10.1 Hexadecimal digit to seven-segment LED decoder 62

3.10.2 Sign-magnitude adder 65

3.10.3 Barrel shifter 68

3.10.4 Simplified floating-point adder 69

3.11 Bibliographic notes 73

3.12 Suggested experiments 73

3.12.1 Multi-function barrel shifter 73

3.12.2 Parameterized barrel shifter 74

3.12.3 Dual-priority encoder 74

3.12.4 BCD incrementor 74

3.12.5 Floating-point greater-than circuit 74

3.12.6 Floating-point and signed integer conversion circuit 74

3.12.7 Enhanced floating-point adder 75

4 Regular Sequential Circuit 77

4.1 Introduction 77

4.1.1 D FF and register 78

4.1.2 Basic block system 78

4.1.3 Code development 79

4.1.4 Sequential circuit coding guidelines and style 79

4.2 HDL code of the FF and register 80

4.2.1 D FF 80

4....