Strain-Engineered MOSFETs - C.K. Maiti

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Auteur(s) : C.K. Maiti - T.K. Maiti

Editeur : Taylor & Francis Ltd

Langue : Anglais

Parution : 31/10/2017

Format : Moyen, de 350g à 1kg

Nombre de pages : 320

Expédition : 484

Dimensions : 15.8 x 23.3 x 2.3

ISBN : 1138075604

Résumé :

Introduction. Substrate-Induced Strain Engineering in CMOS Technology. Process-Induced Stress Engineering in CMOS Technology. Electronic Properties of Strain-Engineered Semiconductors. Strain-Engineered MOSFETs. Noise in Strain-Engineered Devices. Technology CAD of Strain-Engineered MOSFETs. Reliability and Degradation of Strain-Engineered MOSFETs. Process Compact Modelling of Strain-Engineered MOSFETs. Process-Aware Design of Strain-Engineered MOSFETs. Conclusions. Index.

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Biographie:
C K Maiti (Author) ,? T K Maiti (Indian Institute of Technology, Kharagpur, India Indian Institute of Technology, Kharagpur Indian Institute of Technology, Kharagpur Indian Institute of Technology, Kharagpur Indian Institute of Technology, Kharagpur) (Author)...

Sommaire:

Currently strain engineering is the main technique used to enhance the performance of advanced silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Written from an engineering application standpoint, Strain-Engineered MOSFETs introduces promising strain techniques to fabricate strain-engineered MOSFETs and to methods to assess the applications of these techniques. The book provides the background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOSFETs at nanoscale.

This book focuses on recent developments in strain-engineered MOSFETS implemented in high-mobility substrates such as, Ge, SiGe, strained-Si, ultrathin germanium-on-insulator platforms, combined with high-k insulators and metal-gate. It covers the materials aspects, principles, and design of advanced devices, fabrication, and applications. It also presents a full technology computer aided design (TCAD) methodology for strain-engineering in Si-CMOS technology involving data flow from process simulation to process variability simulation via device simulation and generation of SPICE process compact models for manufacturing for yield optimization.

Microelectronics fabrication is facing serious challenges due to the introduction of new materials in manufacturing and fundamental limitations of nanoscale devices that result in increasing unpredictability in the characteristics of the devices. The down scaling of CMOS technologies has brought about the increased variability of key parameters affecting the performance of integrated circuits. This book provides a single text that combines coverage of the strain-engineered MOSFETS and their modeling using TCAD, making it a tool for process technology development and the design of strain-engineered MOSFETs.