Asynchronous Circuit Design for VLSI Signal Processing -

. .

Résumé :
Asynchronous Circuit Design for VLSI Signal Processing is a collection of research papers on recent advances in the area of specification, design and analysis of asynchronous circuits and systems. This interest in designing digital computing systems without a global clock is prompted by the ever growing difficulty in adopting global synchronization as the only efficient means to system timing. Asynchronous circuits and systems have long held interest for circuit designers and researchers alike because of the inherent challenge involved in designing these circuits, as well as developing design techniques for them. The frontier research in this area can be traced back to Huffman's publications `The Synthesis of Sequential Switching Circuits' in 1954 followed by Unger's book, `Asynchronous Sequential Switching Circuits' in 1969 where a theoretical foundation for handling logic hazards was established. In the last few years a growing number of researchers have joined force in unveiling the mystery of designing correct asynchronous circuits, and better yet, have produced several alternatives in automatic synthesis and verification of such circuits. This collection of research papers represents a balanced view of current research efforts in the design, synthesis and verification of asynchronous systems.

Sommaire:
Editorial.- Self-Timed Logic Using Current-Sensing Completion Detection (CSCD).- Performance of Iterative Computation in Self-Timed Rings.- High-Level Optimizations in Compiling Process Descriptions to Asynchronous Circuits.- Designing Self-Timed Systems Using Concurrent Programs.- Synthesis of Hazard-Free Control Circuits from Asynchronous Finite State Machines Specifications.- Specification, Synthesis, and Verification of Hazard-Free Asynchronous Circuits.- A Generalized State Assignment Theory for Transformations on Signal Transition Graphs.- Specification and Analysis of Self-Timed Circuits.- Linear Programming for Hazard Elimination in Asynchronous Circuits.- Verification of Asynchronous Interface Circuits with Bounded Wire Delays.