Models for Large Integrated Circuits - Patrick Dewilde

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Résumé :
1. Introduction.- 1.1 Modeling of MOS Devices.- 1.2 Parasitic Models.- 1.3 Background from Algebra.- 1.4 Background from Analysis.- 1.5 Overview of the Book.- 2. Boundary Value Problems in VLSI Modeling.- 2.1 Field Equations.- 2.2 Integral Equations: the MOSFET Case.- 2.3 Integral Equations: Parasitic Capacitance.- 3. Green's Function for Stratified Media.- 3.1 Definition.- 3.2 The Bounded Multilevel Dielectric Problem.- 3.3 The Unbounded Multilevel Dielectric Problem.- 4. Galerkin Boundary Finite Elements.- 4.1 Element and Local Shape Function.- 4.2 An Optimal Solution.- 4.3 Reduction Using Constraints.- 4.4 Evaluation of Green's Function Integrals.- 4.5 Determination of the Number of Terms Required for Green's Function.- 4.6 Results and Comparisons.- 5. Point Collocation and Further Simplifications.- 5.1 Point Collocation.- 5.2 Further Reduction of Point-Collocation Integrals.- 5.3 The Capacitance Matrix.- 6. Reduced Models.- 6.1 Preliminaries.- 6.2 The Generalized Schur Algorithm.- 6.3 Approximation Theory and Error Analysis.- 6.4 Architectures.- 7. Hierarchical Reduced Models.- 7.1 Two Dimensional Ordering.- 7.2 Hierarchical Approximants.- 7.3 The Sparse Inverse Approximation.- 8. On the Modeling of a Short-channel MOSFET below Threshold.- 8.1 Analytical Solution of the Poisson Equation.- 8.2 Boundary Conditions.- 8.3 Discussion.- 9. Parasitic Capacitances and their Linear Approximation.- 9.1 Parallel Conductors.- 9.2 Corners.- 9.3 Crossing Strips.- 9.4 Combination of Corner and Crossing Strips.- 10. Interconnection Resistances.- 10.1 Introduction.- 10.2 Finite Element Method.- 10.3 The Boundary Finite Element Method.- 11. Hybrid Finite Elements.- 11.1 Introduction.- 11.2 Direct Hybrid Field Modeling.- 11.3 Extension to the Poisson Case.- 11.4 Using aScattered Field.- 12. Appendices.- 12.1 Appendix 3.1: Solution of Equation (3.8).- 12.2 Appendix 3.2: Fourier Integral Evaluation.- 12.3 Appendix 4.1: Evaluation of Singular Integrals.- 12.4 Appendix 4.2: Derivation of (4.41).- 12.5 Appendix A.5....

Sommaire:
A modern microelectronic circuit can be compared to a large construction, a large city, on a very small area. A memory chip, a DRAM, may have up to 64 million bit locations on a surface of a few square centimeters. Each new generation of integrated circuit- generations are measured by factors of four in overall complexity -requires a substantial increase in density from the current technology, added precision, a decrease of the size of geometric features, and an increase in the total usable surface. The microelectronic industry has set the trend. Ultra large funds have been invested in the construction of new plants to produce the ultra large-scale circuits with utmost precision under the most severe conditions. The decrease in feature size to submicrons -0.7 micron is quickly becoming availabl- does not only bring technological problems. New design problems arise as well. The elements from which microelectronic circuits are build, transistors and interconnects, have different shape and behave differently than before. Phenomena that could be neglected in a four micron technology, such as the non-uniformity of the doping profile in a transistor, or the mutual capacitance between two wires, now play an important role in circuit design. This situation does not make the life of the electronic designer easier: he has to take many more parasitic effects into account, up to the point that his ideal design will not function as originally planned....