Understanding Behavioral Synthesis - Elliott, John P.

. .

Résumé :
Behavioral Synthesis: A Practical Guide to High-Level Design includes details on new material and new interpretations of old material with an emphasis on practical information. The intended audience is the ASIC (or high-end FPGA) designer who will be using behavioral synthesis, the manager who will be working with those designers, or the engineering student who is studying leading-edge design techniques. Today's designs are creating tremendous pressures for digital designers. Not only must they compress more functionality onto a single IC, but this has to be done on shorter schedules to stay ahead in extremely competitive markets. To meet these opposing demands, designers must work at a new, higher level of abstraction to efficiently make the kind of architectural decisions that are critical to the success of today's complex designs. In other words, they must include behavioral design in their flow. The biggest challenge to adopting behavioral design is changing the mindset of the designer. Instead of describing system functionality in great detail, the designer outlines the design in broader, more abstract terms. The ability to easily and efficiently consider multiple design alternatives over a wide range of cost and performance is an extremely persuasive reason to make this leap to a high level of abstraction. Designers that learn to think and work at the behavioral level will reap major benefits in the resultant quality of the final design. But such changes in methodology are difficult to achieve rapidly. Education is essential to making this transition. Many designers will recall the difficulty transitioning from schematic-based design to RTL design. Designers that were new to the technology often felt that they had not been told enough about how synthesis worked and that they were not taught how to effectively write HDL code that would synthesize efficiently. Using this unique book, a designer willunderstand what behavioral synthesis tools are doing (and why) and how to effectively describe their designs that they are appropriately synthesized. CD ROM INCLUDED! The accompanying CD-ROM contains the source code and test benches for the three case studies discussed in Chapters 14, 15 and 16.

Sommaire:
1. How Did We Get Here?.- 1.1 Step Back in Time.- 1.2 The Year is 1981....- 1.3 The Year is 1986....- 1.4 The Year is 1991....- 1.5 Today....- 2. An Introduction to Behavioral Synthesis.- 2.1 Why Behavioral Synthesis?.- 2.2 The RTL Design Process.- 2.3 The Behavioral Design Process.- 2.4 Summary.- 3. The Behavioral Synthesis Process.- 3.1 The Behavioral Synthesis Process.- 3.2 Internal Representations.- 3.3 Resource Allocation.- 3.4 Scheduling.- 3.5 Register Allocation.- 3.6 Binding.- 3.7 Data Path and State Machine Extraction.- 3.8 Netlisting.- 3.9 Summary.- 4. Data Types.- 4.1 Synthesis Considerations.- 4.2 bit / bit_vector Types.- 4.3 boolean Type.- 4.4 std_logic / std_logic_vector / signed / unsigned Types.- 4.5 Integer Type.- 4.6 Enumerated Type.- 4.7 Record Type.- 4.8 Array Type.- 4.9 Types Not Supported for Synthesis.- 4.10 Summary.- 5. Entities, Architectures, and Processes.- 5.1 The Entity Declaration.- 5.2 The Architecture Specification.- 5.3 Processes.- 5.4 Summary.- 6. Loops.- 6.1 Loops in RTL Design.- 6.2 Loop Constructs and State Machines.- 6.3 The EXIT Statement.- 6.4 Types of Loops.- 6.5 The NEXT Statement.- 6.6 Scheduling Loops.- 6.7 Loop Unrolling.- 6.8 Summary.- 7. I/O Scheduling Modes.- 7.1 Overview of Scheduling Modes.- 7.2 Cycle-Fixed Scheduling Mode.- 7.3 Superstate-Fixed Scheduling Mode.- 7.4 Free-Floating Scheduling Mode.- 7.5 Summary.- 8. Pipelining.- 8.1 Types of Pipelining.- 8.2 Pipelined Components.- 8.3 Loop Pipelining.- 8.4 Summary.- 9. Memories.- 9.1 Memories in RTL Design.- 9.2 Mapping Arrays to Memory.- 9.3 Summary.- 10. Functions, Procedures, and Packages.- 10.1 Subprograms.- 10.2 Functions.- 10.3 Procedures.- 10.4 Packages.- 10.5 Summary.- 11. Handshaking.- 11.1 Communication With External Models.- 11.2 Handshaking.- 11.3 InterprocessCommunication.- 11.4 Summary.- 12. Reusable Test Benches.- 12.1 Objectives.- 12.2 I/O Timing.- 12.3 Interface Type Considerations.- 12.4 Test Bench Structure.- 12.5 Messages.- 12.6 Summary.- 13. Coding For Behavioral Synthesis.- 13.1 Overview.- 13.2 Entities, Architectures, and Processes.- 13.3 Data Types.- 13.4 Coding Style and I/O Scheduling Mode.- 13.5 Fixed I/O Scheduling Mode.- 13.6 Superstate I/O Scheduling Mode.- 13.7 Free Scheduling Mode.- 13.8 Summary.- 14. Case Study: JPEG Compression.- 14.1 Introduction.- 14.2 The Algorithm.- 14.3 The Environment.- 14.4 Compression Results.- 14.5 Behavioral Description.- 14.6 Behavioral Synthesis.- 14.7 Summary.- 15. Case Study: FIR Filter.- 15.1 Introduction.- 15.2 The Algorithm.- 15.3 Behavioral Description.- 15.4 The Environment.- 15.5 Behavioral Synthesis.- 15.6 Summary.- 16. Case Study: Viterbi Decoding.- 16.1 Introduction.- 16.2 The Algorithm.- 16.3 Behavioral Description.- 16.4 The Environment.- 16.5 Decoding Results.- 16.6 Behavioral Synthesis.- 16.7 Summary.- Appendix A: JPEG Source Code.- Appendix B: FIR Filter Source Code.- Appendix C: Viterbi Source Code.- References and Resources.- CD-ROM.- CD-ROM Contents.- CD-ROM License Agreement.