Digital System Design with FPGA - Unsalan, Cem

. .

Résumé :
1 Introduction
1.1 Hardware Description Languages
1.2 FPGA Boards and Software Tools
1.3 Topics to Be Covered in the Book
2 Field-Programmable Gate Arrays
2.1 A Brief Introduction to Digital Electronics
2.1.1 Bit Values as Voltage Levels
2.1.2 Transistor as a Switch
2.1.3 Logic Gates from Switches
2.2 FPGA Building Blocks
2.2.1 Layout of the Xilinx Artix-7 XC7A35T FPGA
2.2.2 Input/Output Blocks
2.2.3 Configurable Logic Blocks
2.2.4 Interconnect Resources
2.2.5 Block RAM
2.2.6 DSP Slices
2.2.7 Clock Management
2.2.8 The XADC Block
2.2.9 High-Speed Serial I/O Transceivers
2.2.10 Peripheral Component Interconnect Express Interface
2.3 FPGA-Based Digital System Design Philosophy
2.3.1 How to Think While Using FPGAs
2.3.2 Advantages and Disadvantages of FPGAs
2.4 Usage Areas of FPGAs
2.5 Summary
2.6 Exercises
3 Basys3 and Arty FPGA Boards
3.1 The Basys3 Board
3.1.1 Powering the Board
3.1.2 Input/Output
3.1.3 Configuring the FPGA
3.1.4 Advanced Connectors
3.1.5 External Memory
3.1.6 Oscillator/Clock
3.2 The Arty Board
3.2.1 Powering the Board
3.2.2 Input/Output
3.2.3 Configuring the FPGA
3.2.4 Advanced Connectors
3.2.5 External Memory
3.2.6 Oscillator/Clock
3.3 Summary
3.4 Exercises
4 The Vivado Design Suite
4.1 Installation and the Welcome Screen
4.2 Creating a New Project
4.2.1 Adding a Verilog File
4.2.2 Adding a VHDL File
4.3 Synthesizing the Project
4.4 Simulating the Project
4.4.1 Adding a Verilog Testbench File
4.4.2 Adding a VHDL Testbench File
4.5 Implementing the Synthesized Project
4.6 Programming the FPGA
4.6.1 Adding the Basys3 Board Constraint File to the Project
4.6.2 Programming the FPGA on the Basys3 Board
4.6.3 Adding the Arty Board Constraint File to the Project
4.6.4 Programming the FPGA on the Arty Board
4.7 Vivado Design Suite IP Management
4.7.1 Existing IP Blocks in Vivado
4.7.2 Generating a Custom IP
4.8 Application on the Vivado Design Suite
4.9 Summary
4.10 Exercises
5 Introduction to Verilog and VHDL
5.1 Verilog Fundamentals
5.1.1 Module Representation
5.1.2 Timing and Delays in Modeling
5.1.3 Hierarchical Module Representation
5.2 Testbench Formation in Verilog
5.2.1 Structure of a Verilog Testbench File
5.2.2 Displaying Test Results
5.3 VHDL Fundamentals
5.3.1 Entity and Architecture Representations
5.3.2 Dataflow Modeling
5.3.3 Behavioral Modeling
5.3.4 Timing and Delays in Modeling
5.3.5 Hierarchical Structural Representation
5.4 Testbench Formation in VHDL
5.4.1 Structure of a VHDL Testbench File
5.4.2 Displaying Test Results
5.5 Adding an Existing IP to the Project
5.5.1 Adding an Existing IP in Verilog
5.5.2 Adding an Existing IP in VHDL
5.6 Summary
5.7 Exercises
6 Data Types and Operators
6.1 Number Representations
6.1.1 Binary Numbers
6.1.2 Octal Numbers
6.1.3 Hexadecimal Numbers
6.2 Negative Numbers
6.2.1 Signed Bit Representation
6.2.2 One's Complement Representation
6.2.3 Two's Complement Representation
6.3 Fixed- and Floating-Point Representations
6.3.1 Fixed-Point Representation
6.3.2 Floating-Point Representation
6.4 ASCII Code
6.5 Arithmetic Operations on Binary Numbers
6.5.1 Addition
6.5.2 Subtraction
6.5.3 Multiplication
6.5.4 Division
6.6 Data Types in Verilog
6.6.1 Net and Variable Data Types
6.6.2 Data Values
6.6.3 Naming a Net or Variable
6.6.4 Defining Constants and Parameters
6.6.5 Defining Vectors
6.7 Operators in Verilog
6.7.1 Arithmetic Operators<...

Biographie:
FPGA architecture including programmable logic, block RAM, DSP slices, FPGA clock management, and programmable I/O...

Sommaire:
1 Introduction
1.1 Hardware Description Languages
1.2 FPGA Boards and Software Tools
1.3 Topics to Be Covered in the Book
2 Field-Programmable Gate Arrays
2.1 A Brief Introduction to Digital Electronics
2.1.1 Bit Values as Voltage Levels
2.1.2 Transistor as a Switch
2.1.3 Logic Gates from Switches
2.2 FPGA Building Blocks
2.2.1 Layout of the Xilinx Artix-7 XC7A35T FPGA
2.2.2 Input/Output Blocks
2.2.3 Configurable Logic Blocks
2.2.4 Interconnect Resources
2.2.5 Block RAM
2.2.6 DSP Slices
2.2.7 Clock Management
2.2.8 The XADC Block
2.2.9 High-Speed Serial I/O Transceivers
2.2.10 Peripheral Component Interconnect Express Interface
2.3 FPGA-Based Digital System Design Philosophy
2.3.1 How to Think While Using FPGAs
2.3.2 Advantages and Disadvantages of FPGAs
2.4 Usage Areas of FPGAs
2.5 Summary
2.6 Exercises
3 Basys3 and Arty FPGA Boards
3.1 The Basys3 Board
3.1.1 Powering the Board
3.1.2 Input/Output
3.1.3 Configuring the FPGA
3.1.4 Advanced Connectors
3.1.5 External Memory
3.1.6 Oscillator/Clock
3.2 The Arty Board
3.2.1 Powering the Board
3.2.2 Input/Output
3.2.3 Configuring the FPGA
3.2.4 Advanced Connectors
3.2.5 External Memory
3.2.6 Oscillator/Clock
3.3 Summary
3.4 Exercises
4 The Vivado Design Suite
4.1 Installation and the Welcome Screen
4.2 Creating a New Project
4.2.1 Adding a Verilog File
4.2.2 Adding a VHDL File
4.3 Synthesizing the Project
4.4 Simulating the Project
4.4.1 Adding a Verilog Testbench File
4.4.2 Adding a VHDL Testbench File
4.5 Implementing the Synthesized Project
4.6 Programming the FPGA
4.6.1 Adding the Basys3 Board Constraint File to the Project
4.6.2 Programming the FPGA on the Basys3 Board
4.6.3 Adding the Arty Board Constraint File to the Project
4.6.4 Programming the FPGA on the Arty Board
4.7 Vivado Design Suite IP Management
4.7.1 Existing IP Blocks in Vivado
4.7.2 Generating a Custom IP
4.8 Application on the Vivado Design Suite
4.9 Summary
4.10 Exercises
5 Introduction to Verilog and VHDL
5.1 Verilog Fundamentals
5.1.1 Module Representation
5.1.2 Timing and Delays in Modeling
5.1.3 Hierarchical Module Representation
5.2 Testbench Formation in Verilog
5.2.1 Structure of a Verilog Testbench File
5.2.2 Displaying Test Results
5.3 VHDL Fundamentals
5.3.1 Entity and Architecture Representations
5.3.2 Dataflow Modeling
5.3.3 Behavioral Modeling
5.3.4 Timing and Delays in Modeling
5.3.5 Hierarchical Structural Representation
5.4 Testbench Formation in VHDL
5.4.1 Structure of a VHDL Testbench File
5.4.2 Displaying Test Results
5.5 Adding an Existing IP to the Project
5.5.1 Adding an Existing IP in Verilog
5.5.2 Adding an Existing IP in VHDL
5.6 Summary
5.7 Exercises
6 Data Types and Operators
6.1 Number Representations
6.1.1 Binary Numbers
6.1.2 Octal Numbers
6.1.3 Hexadecimal Numbers
6.2 Negative Numbers
6.2.1 Signed Bit Representation
6.2.2 One's Complement Representation
6.2.3 Two's Complement Representation
6.3 Fixed- and Floating-Point Representations
6.3.1 Fixed-Point Representation
6.3.2 Floating-Point Representation
6.4 ASCII Code
6.5 Arithmetic Operations on Binary Numbers
6.5.1 Addition
6.5.2 Subtraction
6.5.3 Multiplication
6.5.4 Division
6.6 Data Types in Verilog
6.6.1 Net and Variable Data Types
6.6.2 Data Values
6.6.3 Naming a Net or Variable
6.6.4 Defining Constants and Parameters
6.6.5 Defining Vectors
6.7 Operators in Verilog
6.7.1 Arithmetic Operators<...