Jeffers, J: Intel Xeon Phi Coprocessor High Performance Prog -

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Résumé :
Intel Xeon Phi Coprocessor High Performance Programming is a practical guide to code development for Intel MIC architecture based products, in particular the first Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques that are essential to programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high-performance microprocessors. Applying these techniques will generally increase your program performance on any system and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture.

The book starts by providing a brief level setting overview of Xeon Phi and Intel? MIC architecture and then quickly uses simple but informative code examples to explain the unique aspects of this new highly parallel and high-performance computational product. It then dives deeper into the meat of the hardware and software architecture behind the high performing examples, explaining the tools, development environment, and coding best practices to successfully leverage wide vectors, many cores, many threads and high bandwidth cache/memory architecture.

Biographie:
Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years. James Reinders is involved in multiple engineering, research and educational efforts to increase use of parallel programming throughout the industry. James has contributed to numerous projects including the world's first TeraFLOP/s supercomputer (ASCI Red) and the world's first TeraFLOP/s microprocessor (Intel Xeon PhiT coprocessor). James has authored numerous technical books, including three other books currently in print: Structured Parallel Programming (Morgan Kaufmann, 2012), Intel Xeon PhiT Coprocessor High Performance Programming (Morgan Kaufmann, 2013), and Multithreading for Visual Effects (2014).

The authors.are uniquely experienced in software development for this new silicon. As a result, this book is the definitive programming reference for the 60+ core monster from Intel.highly readable and interlaced with lots of code examples.--DrDobbs.com, April 2, 2013 This book belongs on the bookshelf of every HPC professional. Not only does it successfully and accessibly teach us how to use and obtain high performance on the Intel MIC architecture, it is about much more than that. It takes us back to the universal fundamentals of high-performance computing including how to think and reason about the performance of algorithms mapped to modern architectures, and it puts into your hands powerful tools that will be useful for years to come. -Robert J. Harrison, Institute for Advanced Computational Science, Stony Brook University, from the Foreword The book benefits software engineers, scientific researchers, and high performance and supercomputing developers in need of high-performance computing resources.--HPCwire.com, March 31, 2013