Computer Memories 1 - Philippe Darche
- Format: Relié Voir le descriptif
Vous en avez un à vendre ?
Vendez-le-vôtreSoyez informé(e) par e-mail dès l'arrivée de cet article
Créer une alerte prix
- Payez directement sur Rakuten (CB, PayPal, 4xCB...)
- Récupérez le produit directement chez le vendeur
- Rakuten vous rembourse en cas de problème
Gratuit et sans engagement
Félicitations !
Nous sommes heureux de vous compter parmi nos membres du Club Rakuten !
TROUVER UN MAGASIN
Retour
Avis sur Computer Memories 1 de Philippe Darche Format Relié - Livre Informatique
0 avis sur Computer Memories 1 de Philippe Darche Format Relié - Livre Informatique
Les avis publiés font l'objet d'un contrôle automatisé de Rakuten.
Présentation Computer Memories 1 de Philippe Darche Format Relié
- Livre Informatique
Résumé : Quotation ix Chapter 1. The Memory Function 1 Chapter 2. Internal Organization of a Random-Access Semiconductor Memory 41 Chapter 3. Additional Functional Blocks 83 Chapter 4. Advanced Internal Organization 93 Chapter 5. External Aspects of a Memory System 115 Chapter 6. Additional Concepts 143 Conclusion 159
Preface xi
Introduction xv
1.1. Main characteristics 1
1.1.1. Memory medium 1
1.1.2. Storage capacity and units of measurement 2
1.1.3. Organization 5
1.1.4. Access policies 6
1.1.5. Types of access 8
1.1.6. Data permanence 8
1.1.7. Timing characteristics 8
1.2. Modeling 12
1.3. Technological and historical aspects 13
1.3.1. Mechanical calculator technologies 14
1.3.2. Main memory technologies in modern computers 14
1.4. Memory in a microcomputer 27
1.5. Memory hierarchization 31
1.6. Conclusion 40
2.1. Basic internal organization 42
2.2. Detailed internal organization 53
2.2.1. Static logic versus dynamic logic 53
2.2.2. Column charge and precharge systems 58
2.2.3. The delay line 62
2.2.4. The address transition detector 63
2.2.5. The data-transition detector 64
2.2.6. Address decoding 64
2.2.7. The column selector 70
2.2.8. The sense amplifier 73
2.2.9. The write circuitry 81
2.3. Conclusion 81
3.1. The phase-locked loop 83
3.2. The delay-locked loop 83
3.3. Internal voltage generators 85
3.3.1. Wordline boost circuit 86
3.3.2. Mid-VDD generator 88
3.3.3. Internal voltage regulators 89
3.4. Implementation 90
3.5. Conclusion 92
4.1. Data format expansion 93
4.2. Block partitioning 93
4.3. Bank partitioning 95
4.4. Multithreaded architectures 98
4.5. Conclusion 113
5.1. Interfacing 115
5.1.1. Basic control signals 115
5.1.2. Signal conditioning 118
5.1.3. Address decoding 119
5.1.4. Serial interfaces 123
5.1.5. Multiple-access memory 124
5.2. External performance improvements 131
5.2.1. Data width increase 131
5.2.2. Capacity increase 132
5.2.3. Rank organization 132
5.2.4. Interleaving and address offset 133
5.3. Coupling 141
5.4. Conclusion 141
6.1. Data alignment 143
6.2. Information storage order: a matter of endianness! 145
6.3. Memory topography of a computer system 150
6.4. EDAC 152
6.5. Conclusion 157
Appendix 1 163
Appendix 2 193
List of Acronyms 207
References 223
Index 241
Biographie: Philippe Darche is Lecturer in Computer Science at the University Institute of Technology (IUT) of Paris - Rives de Seine and Researcher in the Distributed Algorithms and Systems (DeLyS) team at LIP6, Sorbonne University, France. He is also the author of fifteen books on computer architecture.
Sommaire: Quotation ix Preface xi Introduction xv Chapter 1 The Memory Function 1 1.1 Main characteristics 1 1.1.1 Memory medium 1 1.1.2 Storage capacity and units of measurement 2 1.1.3 Organization 5 1.1.4 Access policies 6 1.1.5 Types of access 8 1.1.6 Data permanence 8 1.1.7 Timing characteristics 8 1.2 Modeling 12 1.3 Technological and historical aspects 13 1.3.1 Mechanical calculator technologies 14 1.3.2 Main memory technologies in modern computers 14 1.4 Memory in a microcomputer 27 1.5 Memory hierarchization 31 1.6 Conclusion 40 Chapter 2 Internal Organization of a Random-Access Semiconductor Memory 41 2.1 Basic internal organization 42 2.2 Detailed internal organization 53 2.2.1 Static logic versus dynamic logic 53 2.2.2 Column charge and precharge systems 58 2.2.3 The delay line 62 2.2.4 The address transition detector 63 2.2.5 The data-transition detector 64 2.2.6 Address decoding 64 2.2.7 The column selector 70 2.2.8 The sense amplifier 73 2.2.9 The write circuitry 81 2.3 Conclusion 81 Chapter 3 Additional Functional Blocks 83 3.1 The phase-locked loop 83 3.2 The delay-locked loop 83 3.3 Internal voltage generators 85 3.3.1 Wordline boost circuit 86 3.3.2 Mid-VDD generator 88 3.3.3 Internal voltage regulators 89 3.4 Implementation 90 3.5 Conclusion 92 Chapter 4 Advanced Internal Organization 93 4.1 Data format expansion 93 4.2 Block partitioning 93 4.3 Bank partitioning 95 4.4 Multithreaded architectures 98 4.5 Conclusion 113 Chapter 5 External Aspects of a Memory System 115 5.1 Interfacing 115 5.1.1 Basic control signals 115 5.1.2 Signal conditioning 118 5.1.3 Address decoding 119 5.1.4 Serial interfaces 123 5.1.5 Multiple-access memory 124 5.2 External performance improvements 131 5.2.1 Data width increase 131 5.2.2 Capacity increase 132 5.2.3 Rank organization 132 5.2.4 Interleaving and address offset 133 5.3 Coupling 141 5.4 Conclusion 141 Chapter 6 Additional Concepts 143 6.1 Data alignment 143 6.2 Information storage order: a matter of endianness! 145 6.3 Memory topography of a computer system 150 6.4 Edac 152 6.5 Conclusion 157 Conclusion 159 Appendix 1 163 Appendix 2 193 List of Acronyms 207 References 223 Index 241