Energy Efficient High Performance Processors de Haj-Yahya, Jawad Format Relié

Energy Efficient High Performance Processors - Haj-Yahya, Jawad

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Présentation Energy Efficient High Performance Processors de Haj - Yahya, Jawad Format Relié
- Livre Littérature Générale

Livre Littérature Générale - Haj-Yahya, Jawad - 31/03/2018 - Relié - Langue : Anglais

Auteur(s) : Haj-Yahya, Jawad - Chattopadhyay, Anupam - Ben Asher, Yosi - Mendelson, Avi

Editeur : Springer Singapore

Langue : Anglais

Parution : 31/03/2018

Format : Moyen, de 350g à 1kg

Nombre de pages : 180.0

ISBN : 9789811085536

Biographie:

Jawad Haj-Yahya received his BSc degree in Computer Science from Technion - Israel Institute of Technology, and his MSc and PhD degrees in Computer Science from the University of Haifa. Jawad worked as a power management architect for high-performance processors (Sandy Bridge, Haswell, Skylake, etc) in the Processors' Architecture group at the Intel Corporation for 13 years. Jawad's honors include the Intel Achievement Award (IAA), which is the highest award at Intel. His research interests include energy aware computing, power estimation and applications, and low power IC design. Recently Jawad has joined Nanyang Technology University at Singapore as a cyber security research scientist.

Prof. Avi Mendelson has a blend of industrial and academic experience in several different areas, such as computer architecture, operating systems, power management, reliability, high-performance computing and hardware security. He received his PhD from the ECE Department, University of Massachusetts at Amherst (UMASS) in 1990 and his BSc and MSc degrees from the Computer Science Department, Technion. He was the manager of the academic outreach program at Microsoft R&D Israel, where he initiated various innovation-based activities for students. Before that, he worked for 11 years as a senior researcher and principal engineer at Intel. Among his achievements at Intel, he was the chief architect of the CMP (multicore-on-chip) feature of the first dual-core processors Intel developed, for which he received the Intel Achievement Award (the highest award at Intel). Mendelson has published more than 130 papers in refereed journals, and at conferences and workshops. He completed a full term as an associate editor of IEEE Computer Architecture Letters (CAL) and now serves as an associate editor of IEEE Transactions on Computers.

He served as program chair of a number of major conferences and as the general chair of the ISCA (International Symposium on Computer Architecture) in 2013. Recently he was elected to the Board of Governors of the IEEE Computer Society.

Prof. Yosi Ben-Asher received his PhD degree in Computer Science from the Hebrew University of Jerusalem. He is a professor at Computer Science Department, University of Haifa. He is currently leading several research projects including: P2NC a system to study probabilistic evaluation of Boolean circuits, a high-level synthesis compiler from C to Verilog with optimized memory layout, a silicon compiler that minimizes wire lengths, 1 K multicore chip and an ASIP compiler/CPU based on graph tiling. His research areas include compilers, EDA, parallel programming, ad-hoc networks and reconfigurable networks.

Prof. Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc from ALaRI, Switzerland and PhD from RWTH Aachen, Germany in 2002 and 2008 respectively. From 2008 to 2009, he worked as a member of consulting staff at CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group at RWTH Aachen, as a junior professor. Since September 2014, he has been an Assistant Professor at SCE, NTU.

During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was later commercialized by a leading EDA vendor. He developed several high-level optimizations and verification flows for embedded processors. In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. Together with his doctoral students, Anupam proposed domain-specific, high-level synthesis for cryptography, high-level reliability estimation flows for e...

Sommaire:

Maximizes readers' insights into the power management of modern high-performance processors for energy efficiency

Shares numerous tips for designing robust and scalable power management subsystems for modern system on a chip

Includes a chapter that outlines compiler-assisted methods for power management using modern LLVM compilers with software, firmware, and hardware coordination methods

...

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Energy Efficient High Performance Processors - Haj-Yahya, Jawad

Avis sur Energy Efficient High Performance Processors de Haj - Yahya, Jawad Format Relié - Livre Littérature Générale

Présentation Energy Efficient High Performance Processors de Haj - Yahya, Jawad Format Relié - Livre Littérature Générale

Présentation Energy Efficient High Performance Processors de Haj - Yahya, Jawad Format Relié
- Livre Littérature Générale