Microfluidic Very Large Scale Integration (VLSI) - Madsen, Jan

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Résumé :
This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market....

Biographie:
Paul Pop is a professor at DTU Compute, Technical University of Denmark (DTU). He has received his Ph.D. degree in computer systems from Linkoping University in 2003. His main research interests are in the area of system-level design of embedded systems. He has published extensively in this area, and has received the best paper award at the DATE 2005, RTiS 2007, CASES 2009 and MECO 2013 conferences and the EDAA Outstanding Dissertations Award (co-supervisor) in 2011. Since 2008 he has also addressed Computer-Aided Design methods for biochips. His work in this area has received the best paper award at the CASES 2009 conference. He has co-organized and participated in tutorials and special sessions on CAD for biochips at conferences such as SOCC 2011, ESWEEK 2011, EMBC 2015 and ETS 2015....

Sommaire:
Introduction.- Part 1. Preliminaries.- Design Methodology for Flow-based Microfluidic Biochips.- Biochip Architecture Model.- Biochemical Application Modeling.- Part 2. Compilation.- Compiling High-Level Languages.- Application Mapping and Simulation.- Control Synthesis and Pin-Count Minimization.- Part 3. Physical Design.- Allocation and Schematic Design.- Placement and Routing.- On-Chip Control Synthesis.- Testing and Fault-Tolerant Design.